Table 1: EVD1500 Pin Description
| Pin # | Name | I/O | Description |
| 111 | CLK_VIDEO | I | Pixel clock in all formats except ITU-R BT656. Twice pixel rate in ITU-R BT656 mode. |
| 110, 109 | PROCESS_CTRL_IN[1:0] | I | Control which portion of screen is processed |
| 73, 72, 71, 70, 69, 68, 67, 66 | CLARITY_IN[7:0] | I | Clarity Control |
| 11, 10, 9, 8, 7, 5, 4, 3, 2, 1 | R_CR_IN[9:0] | I | Video component in: see datasheet for details |
| 32, 31, 30, 29, 27, 26, 25, 24, 23, 22 | G_Y_IN[9:0] | I | Video component in: see datasheet for details |
| 65, 63, 62, 61, 60, 59, 58, 57, 56, 55 | B_CB_CRCB_IN[9:0] | I | Video component in: see datasheet for details |
| 113 | HBLNK_IN | I | Horizontal blanking input |
| 112 | VBLNK_IN | I | Vertical blanking input |
| 79 | FIELD_IN | I | Odd/even filed input |
| 78 | HSYNC_IN | I | Horizontal sync input |
| 77 | VSYNC_IN | I | Vertical sync input |
| 80 | WINDOW_ENABLE_IN | I | Window enable input: see datasheet for details |
| 45, 44, 43, 42, 40, 39, 38, 37, 34, 33 | R_CR_OUT[9:0] | I/O | Video component output (mode control input during reset time) |
| 96, 95, 94, 93, 91, 90, 89, 88, 84, 83 | G_Y_OUT[9:0] | O | Video component output |
| 127, 126, 125, 124, 121, 120, 119, 118, 115, 114 | B_CB_CRCB_OUT[9:0] | I/O | Video component output (mode control input during reset time) |
| 14 | HBLNK_OUT | O | Horizontal blanking output |
| 13 | VBLNK_OUT | O | Vertical blanking output |
| 15 | FIELD_OUT | O | Field output |
| 19 | HSYNC_OUT | O | Horizontal sync output |
| 18 | VSYNC_OUT | O | Vertical sync output |
| 17 | WINDOW_ENABLE_OUT | O | Window enable output (refer to datasheet for details) |
| 48 | OUTPUT_ENABLE_N_IN | I | Low to enable R_CR_OUT, G_Y_OUT, B_CB_CRCB_OUT, H/VSYNC_OUT, H/VBLNK_OUT, FIELD_OUT, WINDOW_OUTPUT_ENABLE outputs |
| 50 | SCL | I | Serial configuration bus clock input |
| 51 | SDA | I/O | Serial configuration bus data input/output |
| 49 | CLK_SYSTEM | I | Free-running system clock input |
| 101, 100, 99, 98, 97 | SC_ADD_CTRL_IN[6, 3:0] | I | Controls serial configuration Device Address |
| 82 | SC_ADD_10_BIT_7_BIT_N_IN | I | Controls number of bits in serial configuration Device Address |
| 74 | RESET_N_IN | I | Active low reset input |
| 54, 81 | TEST_IN[1:0] | I | Test inputs (see datasheet for hookup details) |
| 102 | TEST_MODE[0] | I | TEST mode pin (see datasheet for details) |
| 103 | TEST_MODE[1] | I | TEST mode pin (see datasheet for details) |
| 104 | TEST_MODE[2] | I | TEST mode pin (see datasheet for details) |
| 105 | TEST_MODE[3] | I | TEST mode pin (see datasheet for details) |
| 106 | TEST_OUT | O | do not connect |
| 21, 36, 53, 75, 87, 108, 117 | VCC_CORE | I | Core power supply: 1/8V nominal |
| 12, 20, 35, 47, 64, 86, 107, 123 | VCC_BUF | I | I/O buffer power supply: 3.3V nominal |
| 6, 16, 28, 41, 46, 52, 76, 85, 92, 116, 122, 128 | VSS | I | I/O buffer can core ground return |